The present invention relates broadly to a bulk channel CCD apparatus, and in particular, to a split two-phase CCD clocking gate apparatus.
Charge transfer devices may be throughout of as having three functional portions; namely, a signal input portion, where a signal is applied to the device for transforming such signal into a charge packet; a transfer portion, having a plurality of stages where the packet of charge or an accurate portion thereof is transferred from stage to stage; and a readout, output or sensing portion where the charge packet is converted to an electrical signal that is a representation of the charge packet. The operating frequency of charge transfer devices is usually limited by the operating speed of the input and output portions and structures.
The charge-coupled device comprises a capactive semiconductor device having a potential well which can only store an incremental packet of charge. In addition, the charge-coupled device can also transfer that charge packet to an adjacent storage well or to an adjacent similar device. Thus, in a digital system, the presence or absence of a substantially full charge in a potential well, conveniently represents one or the other binary state, wherein data storage and transfer operations may be readily implemented. The charge-coupled devices are particularly advantageous for systems in which sequential processing and storage of long chains of binary values are required, such as in many real time processing and analysis systems. However, there are charge transfer inefficiencies which occur at each storage site, wherein a continuously diminishing charge packet would be transferred if the charge packet were not restored or regenerated periodically to its full level.
The charge-coupled device is essentially a metal-oxide semiconductor capacitor which is biased by an electrical field to create a substrate region that acts as a localized potential minimum for mobile carriers in a charge packet. The transfer of the mobile charge carriers from one storage site to another adjacent side is effected by the proper interrelationships between the voltages on adjacent electrodes. Therefore, it is possible to establish moving potential wells which ultimately carry the charge packets through substrate regions to a device in which the presence or absence of a charge packet is sensed.
The transfer inefficiencies of a charge-coupled device are the result of unavoidable imperfections in semiconductor and device manufacture. There are a number of ways that practitioners in the art have approached the solution to the problem. The most common expedient is to insert active elements in the system, however, this not only substantially increases the power requirements but also requires that a substantial amount of area be devoted to the regeneration function. It is of course desirable that the signal-to-noise ratio be adequately high to correspond to the very high reliability demanded of digital systems. Thus, a charge packet can only be allowed to diminish to that level at which point it may reliably be regenerated without more than a negligible chance of an error occurring, as determined by system reliability requirements. It is clear, however, that the lower the level of charge packet is relative to the 100 percent level, the fewer the number of regenerators that need be used and the greater the packing density of the charge-coupled device array.
The state of the art of single and split phase CCD clocking gate structures is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. Patents and which are incorporated herein by reference:
U.S. Pat. No. 3,796,933 issued to Arnett et al on Mar. 12, 1974; and
U.S. Pat. No. 4,229,752 issued to Hynecek on Oct. 21, 1980.
The Hynecek reference discloses a virtual phase charge transfer device wherein a portion of each cell includes an inversion layer at the semiconductor surface that functions as a virtual electrode shielding that region from any gate induced change in potential. The virtual layer in this reference utilizes a staircase potential. The Arnett et al. reference discloses a charge-coupled semiconductor device for transmitting information in the form of mobile charges through a depletion region which comprises an electrode structure in the surface of a semiconductor body.
In the prior art, virtual phase CCDs are made in shallow buried channels which have proved to be a very high yield technology. The advantages of virtual phase CCDs satisfy the need for a single clocking gate structures which have a very good electrical yield because there are no shorts between multi-phase gates that are contiguous and isolated from each other by several thousand angstroms of oxide. The operation of the virtual phase CCD structure is illustrated in FIG. 1a and 1b.
As the clock goes repulsive, the charge in the left most well in FIG. 1a under the clocked gate 10 spills into the virtual well (the area under the virtual gate). Simultaneously, the charge from the right most clock well (under clock gate 12) spills into the next virtual region (not shown). As the clocked gate is pulsed attractive, the charge from the virtual well moves to the right, that is, from the virtual well into the clocked well located on the right, i.e., under clock gate 12. The advantages of the virtual phase CCD structure is high yield, small pixels at the expense of poor charge handling capacity.
The reason that the charge handling capacity of the virtual phase is lower, is because the clocked well has to swing over a large potential voltage barrier. First, the clocked barrier of the clocked well has to swing below the level of the virtual well region. Secondly, this clocked potential well has to swing above the potential of the virtual barrier. These levels are illustrated in FIG. 1b which is a potential well diagram for the CCD structure of FIG. 1a. Therefore, if the barrier in the clocked region is .theta..sub.a and the barrier in the virtual region is .theta..sub.b the clocked well has to swing .theta..sub.a +.theta..sub.b volts. If there were two phases with overlapping geometry, for the same charge capacity, the swing will be .theta..sub.a. Clearly, a large penalty in charge capacity is paid with the virtual phase CCD because larger clock swings are needed for a given charge handling capacity. If .theta..sub.a =.dwnarw..sub.b the clock swing relation between virtual phase and two phase are two to one in clock voltage swing. Practically speaking, the clock swing in a CCD is limited to 10-20 vdc so the larger clock swings are not practical to compensate for reduction in charge handling capacity with the virtual phase CCD. A two to one charge handling capacity reduction is a difficult feature to give up. This need not be so if the CCD geometry employed is different from a two-phase and/or a virtual phase CCD geometry. The present invention is directed to achieving the above advantages and results.